1. Field of the Invention
The present invention relates to an integrated circuit for switching clock signals having the same phase spacing and same frequency as one another to clock signals having a non-synchronized clock phase.
2. Description of the Prior Art
A known integrated circuit for switching a clock to a clock having a leading clock phase is disclosed in European Application 88116125.1. In this circuit, a switch-over arrangement is included which contains a shift register ring composed of register cells. Each of these contains a D-flipflop that is fed back into itself via an OR gate and, via another OR gate preceding the reset input, is fed back to all other register cells with the exception of that register cell preceding in shift direction. As a result, an "H" status can occur at only one register cell in the shift register ring. A clock monitoring starts the shift register ring upon initialization and again when none of the register cells outputs a control signal as a consequence of a disturbance.
European Published Application 0 275 406 A1 discloses a method and arrangement for recovering the clock and/or the clock phase of a synchronous or plesiochronic digital signal. The arrangement contains an auxiliary clock generator that generates auxiliary clock signals having the same frequency but a different phase relation. Of these, one is selected as auxiliary data clock or recovered clock in a phase correction circuit. These auxiliary clocks fundamentally deviate in frequency from the auxiliary clock to be formed. A phase sensor checks whether the effective signal edges of the digital signal and of the auxiliary data clock have approached one another to less than a defined chronological spacing. As soon as this is the case, it outputs a correction signal. This initiates a phase shifting of the auxiliary data clock in the phase correction circuit by switching between the derived auxiliary clocks.
As disclosed in German Application P 38 09 606.4, the phase of a binary data signal can be continuously adapted to a central clock. A sequence of auxiliary data signals is generated by clocking the data signal with auxiliary clocks. These auxiliary data signals have phase spacings identical to one another with the frequency of the central clock. One of these serves as an adapted data signal. The selection of this data signal and the phase ensues such that pulse width distortions and jitter of the data signal do not have any influence in the clocking.
In German Application P 38 14 640.1, a method and arrangement for clock recovery from a data signal by continuous adaptation of a locally generated clock to a data signal is disclosed. Here, an auxiliary clock generator generates a sequence of auxiliary clocks. These have approximately the same frequency or have the same frequency corresponding to the bit rate of the data signal. These auxiliary clocks have identical phase spacings. A phase detector compares the data signal to the auxiliary clocks and a control logic selects one of these as clock via a switch-over means. That auxiliary clock, to which a switch can be undertaken synchronously and spike-free is selected.